Pattern Recognition. Gaussian elimination row reduction algorithm. Least approximate edges random guessing, then narrow the gap of possibilities. Memory bank of patterns. Automatic time to time patterns comparison and contrast through child-parent fork hyper threading process.
Child-child process communication. Parent-parent process communication. Parent-child process communication. Child-parent process communication. Cloned process communication. [cCPC] CPU process communication. [CPC] Interprocess process communication. [IPC] Remote process communication. [RPC]
Most of these process are taken place within the cache or a pair of EEPROM [Electronic Erasable Programmable Read Only Memory]. Where a stack of 4,096 bits EEPROM when paired with an another stack of 4,096 bits EEPROM yields 16,777,216 or 16MB cache through both the criss-cross or jig-saw network between the EEPROM pair.
8,192 bits EEPROM x 4,096 bits EEPROM = 33,554,432 bits = 32 MB cache.
8,192 bits EEPROM x 8,192 bits EEPROM = 67,108,864 bits = 64 MB cache.
CMOS complementary metal-oxide semiconductor or TTL transistor transistor logic EEPROM are all a suitable candidates.
Pattern recognition success rate % = number of hits / [number of hits + number of miss] percentage